Next generation wireless products are being designed with modem architectures capable of supporting many wireless protocols. In order to minimize the cost, power, and size of these multi-mode modems, these architectures will be designed for increased software configurability with a minimized set of hardware resources necessary for implementing a set of wireless protocols. The general term Software Definable Radio (SDR) is often used for these new modem architectures.
Cost and power considerations have led to the high use of dedicated hardware designs in today's portable devices, especially for CDMA (Code Division Multiple Access) protocols which require tens of billions of operations per second for baseband signal processing. In particular, modem chip rate processing used in rake receiver structures has traditionally been implemented in highly optimized and customized hardware designs. Such optimized hardware designs are not easily translated to general-purpose architectures found in the SDR. This is primarily because a general-purpose architecture contains a relatively small number of generic parallel operations (e.g., arithmetic logic units, multipliers, timers, etc.), and the large number of parallel operations in dedicated hardware designs must be serialized for the SDR. Since the algorithms and processing steps must be modified, it is important to examine and exploit any possible advantage of the software implementation to minimize any increase in size or power.
Thus, what is needed is a method and apparatus for time-sharing a rake receiver structure. The method and apparatus preferably will minimize any increase in size or power due to a transition from a dedicated hardware configuration to an SDR configuration.